1. Field of the Invention
This invention relates to a circuit for preventing appearance of flicker attributable to conversion from a field signal to a frame signal usually provided by the interlaced scanning, and more particularly to a circuit of the kind above described which improves the response of a feedback-clamping loop and can prevent occurrence of undesirable sagging during the vertical synchronizing period. This invention relates also to a flicker preventive circuit which can reliably prevent appearance of flicker without being adversely affected by the temperature dependences and secular variations of various parts of the field signal-frame signal conversion system and without requiring severe adjustments of such parts.
2. Description of the Prior Art
In television, the so-called interlaced scanning is employed in which a picture is scanned with horizontal scanning lines skipped at a rate of one or more lines so as to minimize the influence of flicker perceptible to the eye. Most widely employed in this field is the 2:1 interlaced scanning in which alternate horizontal scanning lines are skipped during scanning of an even field and an odd field. According to the 2:1 interlaced scanning, a rough picture called a field is produced by one vertical scanning, and two fields are superposed to provide a complete picture called a frame. The field repetition rate is 60 fields per second according to, for example, the NTSC standards, and, in this case, the frame repetition rate is 30 frames per second. One frame is completed generally with 525 horizontal scanning lines. The point of beginning of horizontal scanning of an odd field is displaced from that of an even field by 1/2 of one horizontal scanning period or 0.5 H. FIG. 1 shows a typical example of a composite video signal (a frame signal) representing a frame. In FIG. 1, the reference numeral 1 designates a field signal representing an odd field in the composite video signal (the frame signal), and 2 designates a field signal representing an even field in the composite video signal (the frame signal). Reference numerals 3, 4, 5, 6, 7, 8 and 9 designate a vertical blanking period, front equalizing pulses, a vertical synchronizing signal, serrating pulses, back equalizing pulses, a horizontal synchronizing signal, and a video signal, respectively. A portion A in FIG.1 is shown in an enlarged scale in FIG. 2. In FIG. 2, reference numerals 10, 11, 12, 13 and 14 designate a horizontal blanking period, a front porch, a back porch, a pedestal level, and a sync tip level, respectively.
In recording a video signal on a magnetic tape, a magnetic disk or any other recording medium, it is customary that a signal of one field is allotted to one track or a signal of one frame is allotted to one track. Also, the one-field/one-track recording method is classified into the so-called one-frame/two track recording method in which an odd field and an even field constituting a frame are sequentially recorded on adjacent two tracks respectively and the so-called one-field recording method in which only one of an odd field and an even field only is recorded on one track.
In the case of reproduction of a record recorded according to the one-field recording method, the so-called field/frame conversion mode is most frequently employed in which, utilizing the strong vertical correlation of horizontal scanning lines in a video signal is utilized, the same track is scanned twice to reproduce a frame signal from a field signal of one kind. This field/frame conversion mode is intended principally to improve the recording density so as to enable long-time recording in the case of a movie recording and to increase the number of pictures in the case of a still recording. However, in the case of conversion from a field signal to a frame signal, the effect of interlaced scanning cannot be realized by merely repeatedly reproducing the same field signal twice. This is because mere repetition of reproduction of the same field signal twice cannot provide the relative time lag of 0.5 H although this relative time lag of 0.5 H is actually required between the odd field 1 and the even field 2 in FIG. 1 for the purpose of attaining the effect of interlaced scanning, as will be readily seen from the relation between the vertical synchronizing signal 5 and the horizontal scanning signal 8 as well as the video signal 9 in the individual lines.
With a view to realize the effect of interlaced scanning, it is a common practice to attain conversion from a field signal to a frame signal in a manner as shown in FIG. 3. Referring to FIG. 3, the same field signal repeatedly reproduced is passed or not passed through a 0.5-H delay line 15, and an analog switch 16 is actuated to alternately select the thru field signal 17 and the 0.5-H delayed field signal 18 at a time interval of one vertical scanning period (1 V), thereby attaining the desired conversion from a field signal to a frame signal. However, when the arrangement shown in FIG. 3 is employed directly, there will occur a relative time lag of 0.5 H from 1 V between the vertical synchronizing signals in the field signals. To deal with such a trouble, a method as, for example, shown in FIG. 4 is proposed for selectively changing over the contacts c and d of the analog switch 16. It will be seen in FIG. 4 that, in the period allotted for selection of the thru field signal 17, the portion 19 between the front equalizing pulse period and the back equalizing pulse period is additionally allotted for the selection of the 0.5-H delayed field signal 18. Anyway, for the conversion from a field signal to a frame signal, a circuit as shown in FIG. 3 is employed for alternate selection of the thru field signal and the 0.5-H delayed field signal.
However, due to the fact that the provision of the delay line 15 not only gives rise to a delay of transmission time but also leads to considerably attanuation of the signal and also due to the fact that the offset voltage of the analog switch 16 differs between the two contacts c and d thereof, the converted frame signal includes a signal level difference and a pedestal level difference between the even and odd fields, resulting in appearance of flicker on the reproduced picture. A circuit as shown in FIG. 5 has heretofore been employed so as to prevent appearance of such flicker. Referring to FIG. 5, the prior art flicker preventive circuit includes an amplifier 20, clamping circuits 21, 22, a gain-adjusting potentiometer VR.sub.1 and a clamp-level adjusting potentiometer VR.sub.2 associated with the combination of the 0.5-H delay line 15 and the analog switch 16. In the flicker preventive circuit shown in FIG. 5, the gain of the amplifier 20 is adjusted by the gain-adjusting potentiometer VR.sub.1 so that the converted frame signal has the same signal level in each field, and the clamping level is adjusted by the clamping-level adjusting potentiometer VR.sub.2 so that the converted frame signal has the same pedestal level in each field. The above adjustment is usually made by the hand of the operator. Therefore, the proposed circuit is unfit to meet the severe adjustment requirement of -40 dB or more demanded for preventing flicker and is not also unfit for mass production. Also, because the 0.5-H delay line 15, analog switch 16, amplifier 20 and clamping circuits 21, 22 tend to undergo secular variations in addition to their inherent temperature dependences, it has been unable to completely eliminate appearance of flicker attributable to the temperature dependences and secular variations of those parts even if the appearance of flicker could be eliminated temporarily by adjustment of the potentiometers VR.sub.1 and VR.sub.2.
The applicant has developed already a flicker preventive circuit which can automatically prevent appearance of flicker in such a field signal/frame signal conversion system, regardless of the temperature dependences and secular variations of its components. The outline of the automatic flicker preventive circuit, filed already as Japanese Patent Application No. 58-189202 in 1983, will be described with reference to FIGS. 6 and 7 before describing the present invention in detail. FIG. 6 is a circuit diagram of the proposed automatic flicker preventive circuit, and FIG. 7 illustrates the operation of various parts of FIG. 6. Referring to FIG. 6, the automatic flicker preventive circuit includes a 0.5-H delay line 15, a field-selecting analog switch 16, an AGC loop 23 and a feedback-clamping loop 30. The AGC loop 23 acts to maintain constant the sync tip level (14 in FIG. 2) and includes an automatic gain controller 24, the field-selecting analog switch 16, two input-selecting switches 25, 26, two peak detectors 27, 28, and a differential amplifier 29.
Referring to FIG. 6, the analog switch 16 generates a frame signal shown in FIG. 7(a) as its output, and the inputselecting switches 25 and 26 are turned on/off as shown in FIGS. 7(c) and 7(d) respectively under control of a switch control pulse signal 35, which is shown in FIG. 7(b) and selectively passed through an inverter 36. Consequently, the frame signal is applied to the peak detectors 27 and 28 at a time interval of 1 V as shown in FIGS. 7(e) and 7(f) respectively. Thus, the peak value of, for example, the even field signal detected by one of the peak detectors or the peak detector 27 and the peak value of, for example, the odd field signal detected by the other peak detector 28 are applied to the differential amplifier 29, and the output signal 29a of the differential amplifier 29 indicative of the difference is applied to control the automatic gain controller 24 so as to attain coincidence of the peak values of the even and odd fields. When the peak values are the same and constant, the sync level and the signal level are maintained constant. The time constant selected is such that the AGC loop 23 responds to at least the unit field so that the signal level of a succeeding field signal becomes equal to that of a preceding field signal.
On the other hand, the feedback-clamping loop 30 acts to maintain constant the pedestal level (13 in FIG. 2) and includes a sampling switch 31, an integrating circuit 32 and two clamping circuits 33, 34, besides the field selecting switch 16. FIG. 7(g) shows the sampling timing of the sampling switch 31. Referring to FIG. 6, the sampling switch 32 samples the pedestal level in each horizontal scanning period, and the integrating circuit 32 holds the sampled value and compares it with a reference value Vref.sub.1. The resultant difference signal 32a is applied from the integrating circuit 32 to the clamping circuits 33 and 34 each of which generates an output signal providing the pedestal level, so as to attain coincidence of the pedestal levels in the individual horizontal scanning periods. The time constant of this feedback-clamping loop 30 is selected to be less than several H at the most so that the clamping level can be stabilized within the period of 1 H to 2 H after change-over between the fields. Thus, flicker can be eliminated as early as possible even in the presence of variations in the characteristics of the two clamping circuits 33 and 34. Two capacitors 37 and 38 shown in FIG. 6 are provided for the purpose of DC cut-off.
As described above, according to the flicker preventive circuit developed already by the applicant, the difference between the peak values (the sync tip levels) of an even field and an odd field is detected, and an automatic gain controller is controlled on the basis of the detected difference signal thereby maintaining constant the signal level in each of the fields. Also, according to the above circuit, the pedestal level is sampled at a time interval of one horizontal scanning period (H) to find the difference between the detected pedestal level and a reference value, and the clamping level is controlled on the basis of the detected difference signal thereby maintaining constant the pedestal level in each of the horizontal scanning periods. Therefore, temperature dependences and secular variations that may be present in the components of the field signal-frame signal conversion system would not exert any substantial influence on the operation of the flicker preventive circuit, and appearance of flicker is minimized. Further, the flicker preventive circuit can be useful for mass-production since the signal level and the pedestal level can be automatically adjusted.
Although the flicker preventive circuit developed by the applicant has been advantageous in various aspects, there have still been two points to be improved. In the first place, its feedback-clamping loop has been found to be improved. More precisely, in the form shown in FIG. 6, the pedestal level cannot be sampled in the vertical scanning period when a sampling pulse signal produced in synchronism with HD pulses derived from a syncrhonizing signal generator (SSG) is used for turning on/off the sampling switch 31. Accordingly, instead of making sampling of the pedestal level in the vertical scanning period, the voltage holding time of the integrating circuit 32 must be extended to about 4H so as to deal with the above situation. However, this leads to a problem of occurrence of a sag in the vertical scanning period and leads also to a problem of delayed response of the feedback-clamping loop. Also, there arises such a problem that a syncrhonizing signal generator (SSG) and a sampling cancelling circuit are additionally required.
Secondly, the responsiveness of the AGC loop has still had a room to be improved, and, also, the flicker preventive effect tending to be affected by the temperature dependences of the components has still had a room to be improved. More precisely, the holding time of at least 1V required for each of the peak detectors 27 and 28 has limited the response speed of the AGC loop, since these peak detectors 27 and 28 receive their input signals at a time interval of 1V only. Unless the AGC loop can respond sufficiently quickly, the AGC loop may not properly function in response to, for example, on/off of the power source or on/off of the input signal. On the other hand, the peak detectors 27 and 28 are provided independently of each other for detecting the peak values of the thru and delayed field signals respectively. Accordingly, when the temperature dependence of one of the peak detectors differs from that of the other, it leads to appearance of flicker although the flicker may not be so appreciable.